Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of features, presently in the subquarter micron and smaller range, such as horizontal interconnects (typically referred to as lines) and vertical interconnects (typically referred to as contacts or vias; contacts extend to a device on the underlying substrate, while vias extend to an underlying metal layer, such as M1, M2, etc.) in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of reducing the dielectric constant of the many layers and the capacitive coupling between interconnect lines. In order to further improve the speed of integrated circuits, it has become necessary to use materials having low resistivity and low κ(dielectric constant less than 7.0) insulators to reduce the capacitive coupling between adjacent metal lines. The need for low κ materials extends to barrier layers, etch stops, and anti-reflective coatings used in photolithography. However, typical barrier layer, etch stop, and anti-reflective coating materials have dielectric constants that are significantly greater than 7.0 that result in a combined insulator that does not significantly reduce the dielectric constant. Thus, better materials are needed for barrier layers, etch stops, and anti-reflective coatings having low κ values. The need for low κ materials also extends to dielectric layers. For instance, present efforts seek to establish a dielectric constant value for the dielectric layer(s) to less than 3.0 and preferably less than 2.5.
With the increase in circuit density, additional process changes are needed for smaller feature sizes. For instance, efforts are being made to improve the photolithography processes for more precise pattern etching. Photolithography is a technique used in making integrated circuits that uses light patterns and photoresist materials (typically organic polymers) to develop fine-scaled patterns on a substrate surface. Photoresist materials typically include, for example, naphthoquinone diazides. In many instances, to properly process the substrate with photolithography and avoid unwanted patterning, the high reflectivity of the layer to be patterned must be ameliorated so light ray reflection is reduced. Reflectivity is usually expressed as a percentage of a known standard, such as bare silicon, having a value of 100%. Extraneous reflections from underlying layers can be reflected to the photoresist and expose the photoresist in undesired areas. Any unwanted exposure can distort the lines, vias, and other features intended to be formed. The reflectivity of damascene structures, discussed below, has increased the need for better photolithography processes.
With multi-layer structures, increased reflectivity has contributed to imprecise etching. Dielectric layers are naturally translucent to the ultraviolet light used to expose the photoresist. Thus, multi-level dielectrics and features in the damascene structures results in increased and unwanted reflections. As a result, an anti-reflective coating (ARC) is deposited over the layer to be etched, where the ARC is typically a thin sacrificial layer that has a lower reflectivity than the underlying layer and is etched by the same or similar chemistries that are used to etch the underlying layer. The ARC reduces or eliminates the extraneous reflections so that improved feature dimensions and accuracy can be more closely spaced, enabling the increased current density desired for ULSI circuits.
ARC materials can be organic or inorganic, as described in U.S. Pat. No. 5,710,067, which is incorporated by reference herein. Organic ARCs include spin-on polyimides and polysulfones, among other materials, and are generally more expensive and require more complex processing than inorganic ARCs. Inorganic ARCs include silicon nitride, silicon oxynitride, α-carbon, titanium nitride, silicon carbide, and amorphous silicon. Prior to the present invention, inorganic ARCs typically were characterized by a high κ value and were not compatible with low κ structures. Use of a high κ ARC partially negates the advantage of using low κ materials because it adds a high κ material to a stack of otherwise low κ layers. In some applications, the high κ ARC can be removed from the substrate, but the removal adds complexity to the processing sequence. Organic ARCs can be used, but they are generally more expensive and require additional processing.
FIG. 1 shows a representation of a typical substrate with a positive photoresist deposited over a dielectric, as part of the photolithography processing. A positive photoresist develops in the areas exposed to light, whereas a negative photoresist develops in the areas which are not exposed to light. The integrated circuit 10 includes an underlying substrate 12 having a feature 11, such as a contact, via, line, or trench formed thereon. The term “substrate” as used herein can indicate an underlying material, and can be used to represent a series of underlying layers below the layer in question, such as an etch stop or barrier layer. A barrier layer 13 may be deposited over the substrate, followed by a dielectric layer 14. The dielectric layer may be un-doped silicon dioxide also known as un-doped silicon glass (USG), fluorine-doped silicon glass (FSG), or some other low κ material. In this example, an ARC 15 is deposited over the dielectric layer, followed by a photoresist layer 19.
The purpose of the ARC is to reduce or eliminate any reflected light waves, typically, by adjusting three aspects of the ARC material—a refraction index (n), an absorption index (k, distinguished from the “κ” of a “low κ” dielectric), and the thickness (t) of the ARC to create a phase cancellation and absorption of reflected light. Typically, the required n, k, and t values depend on the thickness and properties of the underlying layer and need adjustment for each particular application. A computer simulation program, such as one entitled “The Positive/Negative Resist Optical Lithography Model”, PROLITH/2, v. 4.05, available from Finle Technologies of Austin, Tex., simulates the effect on the n, k, and t values and the reflectivity of the particular layers. The results are analyzed and are typically followed by actual testing and reviewing the results through scanning electron microscopy (SEM) techniques. A proper combination at the various values of n, k, and t is chosen to reduce the reflected light for that application. Because the values of n, k, and t are dependent on each application and each substrate thickness, the proper selection may be time consuming and onerous. In addition, the selection of the n, k, and t values may be only applicable to narrow thickness ranges of the underlying layers which may cause additional difficulties in the repeatability of the deposition process from substrate to substrate.
FIG. 2 is a schematic of the photolithography process in which a light source 23 emits light, such as ultraviolet light, through a patterned template or mask 21 that defines the pattern of light that will be projected onto the photoresist layer 19, ultimately resulting in a patterned substrate. The light typically causes the photoresist in the exposed area 25 to change its solubility to organic solvents. Thus, the exposed areas can be removed by soaking or otherwise cleaning the exposed areas while retaining the unexposed areas.
FIG. 3 is a schematic of the substrate with the feature 27 formed thereon using the etching process. The remainder of the photoresist has been removed, the feature has been etched to the appropriate level, and the substrate is prepared for a subsequent process such as the deposition of a liner, conductor, or other layer(s).
Traditional deposition/etch processes for forming interconnects has also been improved with the higher circuit density to obtain more precise pattern etching. Thus, new processes are being developed. For instance, the traditional method of forming the circuit was depositing blanket layers of a conductor, etching the conductor to pattern the features, and then depositing dielectric materials over and between the features. With the emphasis on increased circuit density, the process has been somewhat reversed by depositing dielectric layers, etching the dielectric layers to form the features, and filling the features with conductive material to form the vias, lines, and other features.
The current trend in metallization is to use a damascene structure. In a dual damascene structure, the dielectric layer is etched to define both the contacts/vias and the interconnect lines in multi-layered substrates. Metal is then inlaid into the defined pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP).
The reflectivity of such multilevel structures as a damascene structure has raised the required level of performance of ARC materials. Prior to such structures, the layer to be etched was typically above a single metal layer which is not transparent to the light exposure. Thus, the unwanted photoresist exposure from underlying layers was substantially limited to the single metal layer under the photoresist. However, in damascene and other structures, an increased number of layers above the conductor layer are now used with multilevel patterning. The dielectric layer(s) and other layers beside the conductor layers in features are comparatively transparent to the exposure light and thus more levels of reflections from multiple levels of features can hinder the photolithography processing of the upper layer. For instance, lines and vias/contacts may appear in the substrate at different levels. Light reflected from the different features at different levels result in reflected light patterns back to the photoresist layer which, unless corrected, may cause unwanted exposure of the photoresist.
Thus, with the decreasing feature sizes, the emphasis on low κ stacks, the use of copper, and the complex dual damascene structures, new methods and materials are needed to provide improved ARC characteristics. Silicon nitride and oxynitride have been typical materials used for an ARC, but have a relatively high dielectric constant (dielectric constant greater than 7.0) and may significantly increase the capacitive coupling between interconnect lines. The capacitive coupling may lead to cross talk and/or resistance-capacitance (RC) delay, i.e., the time required to dissipate stored energy, that degrades the overall performance of the device.
In searching for new materials, others have recognized some potential in silicon carbide (SiC) for some applications. But to the knowledge of the inventor, no source has adequately sought and developed a suitable ARC, barrier layer, and etch stop, using SiC. Furthermore, no known source has found a suitable combination of chemistries that allows in situ deposition, for instance, in the same chamber, of low κ dielectric layers, and SiC barrier layers, etch stops, and ARCs. Some sources, including U.S. Pat. No. 5,710,067 to Foote, et al., above, have noted or suggested silicon carbide in some form as an ARC. To the knowledge of the inventor, silicon carbide that has been produced using these traditional methods has not been effective in meeting the new process requirements in low κ structures. For instance, the disclosed chemistry of U.S. Pat. No. 5,591,566 to Ogawa, which patent is incorporated herein by reference, uses separate sources of silicon, carbon, and hydrogen. This more traditional approach results in a higher κ than is desirable for the low κ emphasis of the ULSI efforts, especially in damascene structures. Another example, disclosed in U.S. Pat. No. 5,360,491 to Carey, et al., which is also incorporated herein by reference, requires a conversion to a crystalline silicon carbide, denoted as β-SiC.
Another reference referring to SiC is U.S. Pat. No. 4,532,150 to Endo et al., which is incorporated herein by reference and refers to a specific formulation of SixC1–x, in which x is a positive number of 0.2 to 0.9 for providing SiC to a substrate surface. Endo provides no disclosure of SiC as a barrier layer, etch stop, or ARC, and the process parameters given in its examples are below the preferred or most preferred parameters of the present invention.
U.S. Pat. No. 5,465,680 to Loboda, incorporated herein by reference, discloses a SiC film in a CVD chamber, but fails to produce the film at low temperatures less than about 600° C. Another Loboda reference, U.S. Pat. No. 5,818,071, also incorporated herein by reference, discloses a SiC film for use as a barrier layer with a low κ dielectric layer, but fails to disclose that the SiC itself may be a low κ material and fails to describe regimes that would produce a low κ SiC. To the inventor's knowledge, a low κ SiC has eluded those in the field until the present invention. Furthermore, the Loboda '071 reference is designed to accommodate a subtractive deposition, not a damascene deposition as current technology uses, in which the substrate deposition deposits the metal layer, then etches the metal and deposits the SiC into the etched metal layer, resulting in a much different structure than a damascene structure.
Another reference, U.S. Pat. No. 5,238,866 to Bolz, et al., also incorporated herein by reference, uses methane, silane, and phosphine to create a hydrogenated silicon carbide coating for use in the medical field, having an improved compatibility with blood. However, none of these references contain a disclosure for SiC with the following process regimes used as a barrier layer, etch stop, or a low κ ARC.
The increasing complexities of the circuitry have also added to the processing steps. Transfers between chambers to effect the processing slow the production process and increase a likelihood of contamination. Thus, the processing would benefit by reducing the transfers outside of an enclosed cluster of chambers or even reducing the transfers out of the processing chamber itself by performing in situ processing on multiple layers. Preferably, the processing would include the same or similar precursors used for the multiple layers, such as the barrier layer(s), etch stop(s), ARC(s), and dielectric layer(s).
Therefore, there is a need for an improved process using silicon carbide as a low κ barrier layer, an etch stop, and an ARC for ICs, especially in a damascene structure and to deposit the layers in situ with each other and with associated dielectric layers.